High frequency ADCs. Press release. Serial Input DAC

Network expansion wireless transmission data using increasingly higher carrier frequencies and data rates poses increasingly pressing challenges to improving signal digitization. This means that the demand for more advanced analog-to-digital converters (ADCs) is increasing. To meet modern requirements, analog-to-digital converters with sampling rates above 1 GHz have emerged. This article will discuss the use of faster ADCs when developing new applications, as well as when upgrading old ones.

Remember the Nyquist rule

When choosing an analog-to-digital converter for a high-frequency device, remember that the ADC sampling rate must be two or more times higher bandwidth signal to be digitized. This sampling rate is called the Nyquist frequency. Note that the term "bandwidth" is used, not "frequency". If the input signal is different from a sine wave, then it is considered complex. For example, a pulse that consists of a main sinusoid and multiple harmonics in accordance with the Fourier theorem. Modulated signals also contain a wide range of frequencies that must be taken into account when choosing the sampling frequency.

Consider a square wave consisting of the fundamental frequency of a sine wave and an infinite number of odd harmonics. For a 300 MHz square wave signal, the ADC sampling frequency must be at least twice the fifth harmonic frequency, or 3 GHz. More complex signals, such as radar or modulated signals, require similarly high processing rates to accurately capture all signal details.

An example is the receiver of LTE Advanced signal processing stations, which use media aggregation for higher throughput and increased data transfer rates. Several standard 20 MHz LTE channels are grouped to provide 40-, 80-, 160 MHz bandwidth to provide higher OFDM throughput.

Application of high-speed ADCs in various systems

The primary applications of high-speed ADCs are in software-defined radio (SDR) devices. Most modern SDRs use a direct conversion (zero IF) architecture, in which the input signal is digitized directly after filtering and amplification. When working with UHF or high frequency signals (UHF or microwave), the analog-to-digital converter must have a high sampling frequency. One example is a cellular base station receiver.

Also, high-speed ADCs can be used in other systems, such as electronic warfare (electronic warfare) systems, RF recording systems, and radar equipment. Very often, high-speed analog-to-digital converters are used in measuring technology and reflectometry (OTDR) equipment. It is an important part of digital predistortion receivers used in linear RF power amplifiers.

Below is the block diagram of the Texas Instruments ADC32RF45 used in direct conversion SDR receivers:

The input bandpass filter selects the desired signal, the low noise amplifier amplifies it, and then the signal is sent to digital amplifier with variable gain that provides the proper input signal level to the A/D converter. Out-of-band filters prevent aliasing. The ADC works with an external PLL synthesizer and jitter cleaner. It connects to the DSP processor using the JESD2048 interface.

Products that use the ADC32RF45 include Pentek's FlexorSet Software Radio Modules. These modules are designed to help engineers design custom communications equipment and experiment with various SDR equipment. The modules offer two ADC channels and two DAC channels (). Xilinx FPGA with internal software for data acquisition and signal generation, the DAC facilitates experimentation.

Design requirements

The most important design step with the ADC32RF45 will be the correct selection of input circuit elements. In particular, out-of-band smoothing filters must match the ADC input impedance. This is essential to ensure maximum in-band flatness of the filter and preferably outside the rejection zone.

To simplify the design, it is recommended to use S parameters (dispersion parameters). S-parameters in the frequency domain are related to quantities that simulate the behavior of radio frequency circuits and components. These complex values ​​are typically represented in a matrix form that can be manipulated to illustrate the behavior and performance of circuits and components. They are preferred when designing systems associated with transmission lines, filters and other high-frequency devices.

Additionally, a complete reference design with evaluation module (EVM) will help speed up and simplify the design process.

09/12/2013 - Norwood, Massachusetts, USA

Analog Devices, Inc. (NASDAQ: ADI) introduced the PulSAR® family of 18-bit analog-to-digital converters (ADCs) with 5 million samples per second (MSPS) throughput, twice the speed of any successive-approximation register available today , SAR). With its industry-leading throughput, best-in-class noise floor, and high linearity, the AD7960 PulSAR ADC is ideal for low-power, multiplexed applications such as digital radiography, and oversampled applications including spectroscopy and gradient control. in magnetic resonance imaging and chromatographic analysis of gases.

Unlike other 18-bit ADCs, where higher sample rates come at the cost of increased power consumption and reduced accuracy, the AD7960 consumes 39 mW at 5 MSPS and is optimized to maintain excellent linearity in static mode (+/- 0.8 LSB integral nonlinearity) and high dynamic characteristics (signal-to-noise ratio 99 dB) even at maximum speed. This new converter also has the best noise floor to full scale ratio of 22.4 nV/√Hz in its class. Small package dimensions help designers meet the stringent size, thermal, and power requirements that come with high-channel-count systems.

Analog Devices also introduced the 16-bit PulSAR AD7961 ADC family, which supports excellent signal-to-noise ratio (95.5 dB) and integral nonlinearity (+/- 0.2 LSB) at 5 MSPS.

• Download datasheet, watch video, order samples and evaluation boards:
• Circuits from the Lab sample design: Precision, low-power, 18-bit signal chain for 5 MSPS data acquisition system
• Connect with other Analog Devices developers and product experts in the online community technical support EngineerZone™:

PulSAR AD7960 and AD7691 ADCs are targeted at data acquisition systems

Pin-compatible PulSAR AD7961 and AD7960 ADCs enable easy-to-modify 16/18-bit data acquisition systems for industrial and healthcare applications. They have a configurable, low-noise LVDS (low-voltage differential signaling) interface that allows data to be received from the converter at speeds up to 300 MHz.

Price and availability for ordering

Product	Sample Availability / Serial Production	Permission	SNR (typ.)	Pace. range	Price per piece when ordering 1000 pieces	Frame
AD7960	Now	18 bit		-40°C to 85°C	$31.00	32-pin LFCSP
AD7961	Now	16 bit	95.5 dB	-40°C to 85°C	$21.00	32-pin LFCSP

The AD7960 can be used with the ADA4897 low-power rail-to-rail amplifier, the AD8031 rail-to-rail amplifier, and the ADR4540 or ADR4550 reference voltage sources for building Full featured, low power, precision signal chain.

• About Analog Devices
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This article discusses the main issues regarding the operating principle of various types of ADCs. At the same time, some important theoretical calculations regarding the mathematical description of analog-to-digital conversion remained outside the scope of the article, but links are provided to which interested reader will be able to find a more in-depth discussion of the theoretical aspects of ADC operation. Thus, the article concerns itself more with understanding the general principles of operation of ADCs than with a theoretical analysis of their operation.

Introduction

As a starting point, let's define analog-to-digital conversion. Analog-to-digital conversion is the process of converting an input physical quantity into its numerical representation. An analog-to-digital converter is a device that performs such a conversion. Formally, the input value of the ADC can be any physical quantity - voltage, current, resistance, capacitance, pulse repetition rate, shaft rotation angle, etc. However, for definiteness, in what follows, by ADC we will mean exclusively voltage-to-code converters.

The concept of analog-to-digital conversion is closely related to the concept of measurement. By measurement we mean the process of comparing the measured value with some standard; with analog-to-digital conversion, the input value is compared with some reference value (usually a reference voltage). Thus, analog-to-digital conversion can be considered as a measurement of the value of the input signal, and all the concepts of metrology, such as measurement errors, apply to it.

Main characteristics of the ADC

The ADC has many characteristics, the main ones being conversion frequency and bit depth. The conversion frequency is usually expressed in samples per second (SPS), and the bit depth is in bits. Modern ADCs can have a bit width of up to 24 bits and a conversion speed of up to GSPS units (of course, not at the same time). The higher the speed and bit capacity, the more difficult it is to obtain the required characteristics, the more expensive and complex the converter. Conversion speed and bit depth are related to each other in a certain way, and we can increase the effective conversion bit depth by sacrificing speed.

Types of ADCs

There are many types of ADCs, but for the purposes of this article we will limit ourselves to considering only the following types:

• Parallel conversion ADC (direct conversion, flash ADC)
• Successive approximation ADC (SAR ADC)
• delta-sigma ADC (charge-balanced ADC)

ADCs of direct (parallel) conversion have the highest speed and lowest bit depth. For example, the parallel conversion ADC TLC5540 from Texas Instruments has a speed of 40MSPS with only 8 bits. ADC of this type can have conversion speeds up to 1 GSPS. It can be noted here that pipelined ADCs have even greater speed, but they are a combination of several ADCs with lower speed and their consideration is beyond the scope of this article.

The middle niche in the bit-rate-speed series is occupied by successive approximation ADCs. Typical values ​​are 12-18 bits with a conversion frequency of 100KSPS-1MSPS.

The highest accuracy is achieved by sigma-delta ADCs with a bit width of up to 24 bits inclusive and a speed from SPS units to KSPS units.

Another type of ADC that has found use in the recent past is the integrating ADC. Integrating ADCs have now been almost completely replaced by other types of ADCs, but can be found in older measuring instruments.

Direct conversion ADC

Direct conversion ADCs became widespread in the 1960s and 1970s, and began to be produced as integrated circuits in the 1980s. They are often used as part of “pipeline” ADCs (not discussed in this article), and have a capacity of 6-8 bits at a speed of up to 1 GSPS.

The direct conversion ADC architecture is shown in Fig. 1

Rice. 1. Block diagram of direct conversion ADC

The operating principle of the ADC is extremely simple: the input signal is supplied simultaneously to all “positive” inputs of the comparators, and a series of voltages are supplied to the “negative” ones, obtained from the reference voltage by dividing them with resistors R. For the circuit in Fig. 1 this row will be like this: (1/16, 3/16, 5/16, 7/16, 9/16, 11/16, 13/16) Uref, where Uref is the ADC reference voltage.

Let a voltage equal to 1/2 Uref be applied to the ADC input. Then the first 4 comparators will work (if you count from below), and logical ones will appear at their outputs. The priority encoder will form a binary code from a “column” of ones, which is captured in the output register.

Now the advantages and disadvantages of such a converter become clear. All comparators operate in parallel, the delay time of the circuit is equal to the delay time in one comparator plus the delay time in the encoder. The comparator and encoder can be made very fast, as a result the whole circuit has very high performance.

But to obtain N bits, 2^N comparators are needed (and the complexity of the encoder also grows as 2^N). Scheme in Fig. 1. contains 8 comparators and has 3 bits, to obtain 8 bits you need 256 comparators, for 10 bits - 1024 comparators, for a 24-bit ADC they would need over 16 million. However, the technology has not yet reached such heights.

successive approximation ADC

A successive approximation register (SAR) analog-to-digital converter measures the magnitude of the input signal by performing a series of sequential “weightings,” that is, comparisons of the input voltage value with a series of values ​​generated as follows:

1. in the first step, the output of the built-in digital-to-analog converter is set to a value equal to 1/2Uref (hereinafter we assume that the signal is in the interval (0 – Uref).

2. if the signal is greater than this value, then it is compared with the voltage lying in the middle of the remaining interval, i.e., in this case, 3/4Uref. If the signal is less than the set level, then the next comparison will be made with less than half of the remaining interval (ie with a level of 1/4Uref).

3. Step 2 is repeated N times. Thus, N comparisons (“weightings”) produce N bits of the result.

Rice. 2. Block diagram of a successive approximation ADC.

Thus, the successive approximation ADC consists of the following nodes:

1. Comparator. It compares the input value and the current value of the “weighting” voltage (in Fig. 2, indicated by a triangle).

2. Digital to Analog Converter (DAC). It generates a voltage “weight” based on the digital code received at the input.

3. Successive Approximation Register (SAR). It implements a successive approximation algorithm, generating the current value of the code fed to the DAC input. The entire ADC architecture is named after it.

4. Sample/Hold scheme (Sample/Hold, S/H). For the operation of this ADC, it is fundamentally important that the input voltage remains constant throughout the conversion cycle. However, “real” signals tend to change over time. The sample-and-hold circuit “remembers” the current value of the analog signal and keeps it unchanged throughout the entire operating cycle of the device.

The advantage of the device is the relatively high conversion speed: the conversion time of an N-bit ADC is N clock cycles. The conversion accuracy is limited by the accuracy of the internal DAC and can be 16-18 bits (24-bit SAR ADCs have now begun to appear, for example, AD7766 and AD7767).

Delta-Sigma ADC

Finally, the most interesting type of ADC is the sigma-delta ADC, sometimes called charge-balanced ADC in the literature. The block diagram of the sigma-delta ADC is shown in Fig. 3.

Fig.3. Block diagram of a sigma-delta ADC.

The operating principle of this ADC is somewhat more complex than that of other types of ADC. Its essence is that the input voltage is compared with the voltage value accumulated by the integrator. Pulses of positive or negative polarity are supplied to the integrator input, depending on the result of the comparison. Thus, this ADC is a simple tracking system: the voltage at the integrator output “tracks” the input voltage (Fig. 4). The result of this circuit is a stream of zeros and ones at the output of the comparator, which is then passed through a digital low-pass filter, resulting in an N-bit result. LPF in Fig. 3. Combined with a “decimator”, a device that reduces the frequency of readings by “decimating” them.

Rice. 4. Sigma-delta ADC as a tracking system

For the sake of rigor of presentation, it must be said that in Fig. Figure 3 shows a block diagram of a first order sigma-delta ADC. The second order sigma-delta ADC has two integrators and two feedback loops, but will not be discussed here. Those interested in this topic can refer to.

In Fig. Figure 5 shows the signals in the ADC at zero input level (top) and at Vref/2 level (bottom).

Rice. 5. Signals in the ADC at different levels input signal.

Now, without delving into complex mathematical analysis, let's try to understand why sigma-delta ADCs have a very low noise floor.

Let's consider the block diagram of the sigma-delta modulator shown in Fig. 3, and present it in this form (Fig. 6):

Rice. 6. Block diagram of a sigma-delta modulator

Here the comparator is represented as an adder that adds the continuous wanted signal and the quantization noise.

Let the integrator have a transfer function 1/s. Then, representing the useful signal as X(s), the output of the sigma-delta modulator as Y(s), and the quantization noise as E(s), we obtain the ADC transfer function:

Y(s) = X(s)/(s+1) + E(s)s/(s+1)

That is, in fact, the sigma-delta modulator is a filter low frequencies(1/(s+1)) for the useful signal, and a filter high frequencies(s/(s+1)) for noise, with both filters having the same cutoff frequency. Noise concentrated in the high-frequency region of the spectrum is easily removed by a digital low-pass filter, which is located after the modulator.

Rice. 7. The phenomenon of “displacement” of noise into the high-frequency part of the spectrum

However, it should be understood that this is an extremely simplified explanation of the phenomenon of noise shaping in a sigma-delta ADC.

So, the main advantage of the sigma-delta ADC is its high accuracy, due to the extremely low level of its own noise. However, to achieve high accuracy, it is necessary that the cutoff frequency of the digital filter be as low as possible, many times less than the operating frequency of the sigma-delta modulator. Therefore, sigma-delta ADCs have low speed transformations.

They can be used in audio engineering, but their main use is in industrial automation for converting sensor signals, in measuring instruments, and in other applications where high accuracy is required. but not required high speed.

A little history

The oldest mention of an ADC in history is probably the Paul M. Rainey patent, "Facsimile Telegraph System," U.S. Patent 1,608,527, Filed July 20, 1921, Issued November 30, 1926. The device depicted in the patent is actually a 5-bit direct conversion ADC.

Rice. 8. First patent for ADC

Rice. 9. Direct conversion ADC (1975)

The device shown in the figure is a direct conversion ADC MOD-4100 manufactured by Computer Labs, manufactured in 1975, assembled using discrete comparators. There are 16 comparators (they are located in a semicircle in order to equalize the signal propagation delay to each comparator), therefore, the ADC has a width of only 4 bits. Conversion speed 100 MSPS, power consumption 14 watts.

The following figure shows an advanced version of the direct conversion ADC.

Rice. 10. Direct conversion ADC (1970)

The 1970 VHS-630, manufactured by Computer Labs, contained 64 comparators, was 6-bit, 30MSPS, and consumed 100 watts (the 1975 version VHS-675 had 75 MSPS and consumed 130 watts).

Literature

W. Kester. ADC Architectures I: The Flash Converter. Analog Devices, MT-020 Tutorial.

Steve Logan (Maxim Integrated)

The abundance of modern analog-to-digital converters (ADCs) confronts the developer with a difficult choice.

Integrated ADCs have a resolution of 8…24 bits and there are even some 32-bit ones. There are ADCs built into microcontrollers, FPGAs, microprocessors, SoCs, successive approximation ADCs (SAR), and sigma-delta versions. Pipeline ADCs are used in applications where the highest sampling rates are required. ADC sampling rates range from 10 samples/s to over 10 GS/s. And the price range is from less than $1 to $265 dollars and more.

To select the best ADC for your application, consider Various types of these products and the optimal conditions of use for their main types.

SAR ADC – for medium speeds and “photographing” data

Successive Approximation Register (SAR) ADCs are available in a wide range of resolutions and speeds. The first, as a rule, lies in the range of 6...8 to 20 bits, the second - from several KSa/s to 10 MS/s. SAR ADCs are a good choice for mid-speed applications such as motor control, vibration analysis, and process monitoring. They are not as fast as pipelined ADCs (discussed next), but they are faster than sigma-delta ADCs (also discussed next).

The range of ADC SAR power dissipation is directly related to the sampling rate. For example, a chip that dissipates 5 mW of power at 1 MSa/s will dissipate 1 μW at 1 kSa/s. Thus, SAR ADCs are quite flexible in terms of application and the designer can use one name for many applications.

Another advantage of SAR ADCs is that they take a “photograph” of the analog input signal. SAR architecture samples at a specific point in time. When might a developer need this? When you need to measure multiple signals at once, you can sample multiple single-channel SAR ADCs simultaneously, or sample simultaneously using a multichannel ADC or multiple storage samplers (T/H-cores) within it. This will allow the system to measure multiple analog signals at the same time.

In current transformers and voltage transformers, SAR ADCs are used in relay protection circuits. With their help, the protection system simultaneously measures different phases of current and voltage. In the utility grid sector, this contributes to more effective management energy networks.

Sigma-Delta ADC – for greater accuracy

If you need increased accuracy through higher sampling levels or maximum effective number of bits (ENOB), a sigma-delta ADC is the best choice, especially for low-noise precision applications. When speed is not so critical, oversampling and noise shaping in a sigma-delta ADC gives very high accuracy.

When the SAR ADC market was just starting to become saturated 5...10 years ago, many analog companies invested in multi-channel sigma-delta cores. Today's result of this process is very high-quality ADCs with a resolution of up to 24 or 32 bits and sampling rates from 10 samples/s to 10 MS/s.

What applications might require more than 20-bit resolution? An example of applications where precision to the maximum possible number of bits is typically required - measuring instruments and fuel chromatographs for the oil and gas industry. As well as other system applications that set the standard for assessing the accuracy of analog signals, applications where end users must have absolute confidence in the data received.

Do you need a modulator?

The latest sigma-delta ADCs have become difficult to categorize in terms of speed and sampling rate. Traditional sigma-delta ADCs performed all digital post-processing internally (including SINC/cut filters, decimation, noise shaping). After this, the data was sequentially outputted out with a very high ENOB (Effective Number of Bits). For example, if you had a 24-bit ADC, the output would be in 24-bit format. The first bit was the most significant bit (MSB), and the 24th was the least significant bit (LSB). The data output speed in a typical case was equal to the system clock speed divided by 24. These were not the fastest or most flexible ADCs.

In the last 5...10 years, sigma-delta modulators have become more popular, in particular in applications requiring increased speed (often about 1 MSa/s or more). Without waiting for the 24-bit output to be fully digitized, the sigma-delta modulator outputs the data stream bit by bit, shifting the task of digital filtering for further data analysis to the processor or FPGA.

This modulator flexibility is useful for applications such as motor control, where 12 to 16 bits may be sufficient. The motor controller may not need the least significant 8 bits of a 24-bit data stream if the first 16 bits provide sufficient analog measurement accuracy.

Serial ADCs vs Sigma-Delta: Speed ​​Is Key

Another important topic to discuss is input filters. Recall that the serial ADC architecture allows you to take a fast frame. When an application requires higher sampling rates, the input filter becomes more complex. Then, in many cases, an external buffer or amplifier is needed to "drive" the input capacitor and quickly dampen the oscillations, and this amplifier must have sufficient bandwidth. Figure 1 shows an example of enabling the MAX11166 500 kSa/s 16-bit serial ADC. The higher the bit depth and the higher the sampling rate, the shorter the period of time required to match the input and correctly read the data.

Figure 1 uses a MAX9632 amplifier with 55 MHz gain bandwidth and a simple RC filter. This particular amplifier delivers noise of less than 1 nV/√Hz, giving a system resolution of 1/10 dB effective bit.

Compared to a SAR ADC, the data from the input of a sigma-delta ADC is read many times, so the anti-aliasing filter requirements are not as critical. Often a simple RC filter is sufficient. Figure 2 shows an example connection for the MAX11270 64 kSa/s 24-bit Sigma-Delta ADC. This is a so-called Wheatstone bridge with a 10 nF capacitor connected between the differential inputs.

Pipeline ADCs – for ultra-high sampling rates

In this article, we have already mentioned pipelined ADCs as being in demand for obtaining the highest sampling rates, for example, in RF applications and SDR - wireless radio with program task frequencies.

Over the past 10 years, the largest manufacturers analog microcircuits actively invested in the development of pipeline ADCs. The two main advantages of pipelined ADCs are speed and power. With sampling rates ranging from 10 MSa/s to several GS/s, the choice of interfaces for these products becomes most critical. A “big battle” is expected around the digital outputs of pipelined ADCs. The parallel interface has so far been proposed as the main one, but the serial LVDS interface is also quite suitable, for example, for ultrasonic applications with a large number of channels and a sampling frequency in the range of 50...65 MSa/s. However, new types of interfaces already exist.

Serial interface JESD204B

JESD204B is a high speed serial interface with data transfer up to 12.5 Gbit/s. Having emerged relatively recently, it allowed ADC manufacturers to significantly increase sampling rates, and processor and FPGA manufacturers with their serial transceivers followed suit.

In a multi-channel application with multiple ADCs running in parallel, the problem is the tangled connections between the ADC and the FPGA/processor. When using the JESD204B interface, the number of data lines is significantly reduced, thereby saving board space. Figure 3 shows a single serial output pair and a clock input of this interface, which significantly reduces the required number of I/O pins.

Power consumption of pipelined ADCs

As product miniaturization continues to increase, leading ADC manufacturers are increasingly striving to reduce power consumption. Good performance - 1 mW per 1 MSa/s. If the performance of your ADC is close to this, then you have something to start from when creating a project.

ADCs optimized for microcontrollers, FPGAs, CPUs and system-on-chips

ADCs built into chips are usually not the most productive. Initially, when a 12-bit ADC was built into a chip, it was assumed that it would operate as an 8-bit ADC to achieve guaranteed effective number of bits (ENOB) values ​​or linearity. To ensure the desired performance of the ADC, the user must carefully review the parameters of the complete specification and determine which of them must have guaranteed values. However, often only standard characteristics or minimum and maximum values parameters from the brief specifications.

Recently, ADC characteristics such as integral nonlinearity (INL), differential nonlinearity (DNL), gain error, and effective number of bits (ENOB) have improved significantly, allowing ADCs to be more widely integrated into microcontrollers, and the number of chips with built-in ADCs has increased significantly. Currently, if an application requires conversion with a resolution of 12 bits or less, or only a few channels of conversion, the most cost-effective solution is a microcontroller.

FPGA manufacturers have also begun to integrate ADCs into their systems. For example, a company Xilinx Places a 12-bit 1 MSa/s ADC in all 7 Series FPGAs and Zynq SoCs. However, the location of the ADC on the board is very important. A processor module with an FPGA or system-on-chip can be located at a considerable distance from the analog input, which can generally be placed on a separate board connected to the processor board via a high-speed digital bus. If you don't want to put sensitive analog signals through this kind of testing, then an on-chip or FPGA ADC is not your choice. In this case, you will definitely need a separate high-quality ADC. For example, for programmable logic controllers (PLCs), this will most likely be a 24-bit sigma-delta ADC.

If we talk about PLC, we should mention such an important element as insulation. Most PLC analog inputs include several forms of isolation, usually digital. Many analog input modules contain low-cost microcontrollers for fast response and interrupts. In this case, the location of the isolation suggests whether an on-chip ADC should be used. If the isolation is between the processor (or microcontroller) and the bus, an on-chip ADC is suitable. If the microcontroller needs to be isolated from high voltage input signals, then the best solution are an integrated ADC and a digital isolator.

Which is the best choice?

We have discussed several characteristics of modern ADCs. How important is the speed, power and accuracy of the signals you measure?

If you need simple, low-resolution readout for home use, ADCs built into a microcontroller, FPGA, processor, or ADC system-on-chip will likely do it. If your application is low speed (the analog input signal is close to DC, such as a slowly varying temperature signal), a sigma-delta ADC is the optimal choice. If the input signal changes quickly enough, as in the case of vibration analysis of a motor running at about 1000 rpm, a serial (SAR) ADC is the best option. If the application needs to measure the fastest changing analog signals available, then the best choice– pipeline ADC.

The main phrase that you should not forget about when choosing an ADC is “it depends on...”. If you are a developer digital circuits or a power supply expert puzzled by choosing the right ADC - you'll explore detailed instructions. ADCs are complex microcircuits with many nuances that require careful study of the technical description and debugging kits. Table 1 shows the minimum and maximum parameters of ADCs available on the market. This is a real picture today. Who knows how it will change in the coming years?

Table 1. Standard range of ADC characteristics

* – modulator output speed

In a direct-weighting ADC design, if the comparators are replaced by linear amplifiers and the output voltages of each are compared using a series of comparators with multiple reference voltages, the input impedance can be increased. True, the number of comparators and logic gates in the decoding circuit will not decrease.

Hewlett-Packard patented new method, called analog decoding, theoretically allowing N-bit analog-to-digital conversion to use only N comparators, latches, and XOR gates.

The method is based on the use of analog decoding circuits operating at several levels, in contrast to conventional comparators operating at one.

2.4. Output coding

In a direct weighing ADC, the outputs of comparators whose reference voltages are less than the input signal are in state 1, and those whose reference voltages are greater than the input signal are in state 0. By analogy with a mercury thermometer, such an output code is called thermometric. When the input signal changes, the state of only one comparator changes at any given time. However, the moments of operation of the latter and the arrival of the clock pulses of the flip-flops-latches are independent, which, at certain ratios of the delays of these elements, can lead to the appearance of instability of the ADC output code, called the “sparking code”. One way to combat this phenomenon is to build a decoding device using a Gray code, in which the state of only one bit can change at a time.

2.5. Peak detection function

In order to record a large fragment of a signal into the limited memory available in the device, the sampling frequency must be reduced compared to the maximum possible. In this case, short signal spikes may be missed. To prevent this phenomenon, you can use the following technique. The sampling rate is always maximum. The result of each Nth sample, where N is the sampling frequency division factor. To highlight the maximum positive voltage in the interval between records, the value of the current sample is constantly compared with the previous one, and the larger one is stored. Similarly, the maximum negative voltage is highlighted. Such "smart" devices using the described recursive algorithm are built into some new digital oscilloscopes. For example, the Hewlett-Packard HP54800 oscilloscope can store pulses of up to 500 ps, ​​which corresponds to a sampling rate of 2 GHz.

Rice. 1. Block diagram of a “classical” direct weighing ADC

Rice. 2. Interpolating structure of direct weighing ADC

With the described algorithm, the minimum duration of the allocated pulse is limited by the time of the full ADC conversion cycle, a significant part of which is spent on converting the output code of a line of comparators into an output signal using a multistage logic circuit. By changing the logic circuit of the ADC, the delay of the latter can be reduced to the delay of one latch trigger. The structure of such a digital peak detector TDC1035 from Raytheon is shown in Fig. 3. It differs from the “classical” one (Fig. 1) in that instead of gated D-triggers, RS-triggers are used here, which are triggered immediately after the arrival of the corresponding comparator signal and remain in this state until the arrival of the reset pulse. The "thermometric" output code of the RS flip-flop bar represents the peak value code of the signal. The time for its transformation into a standard form no longer has strict restrictions. This ADC is made using fairly old technology and has a guaranteed pulse duration measured with full 8-bit precision of 30 ns.

Rice. 3. Block diagram of a peak detector with direct weighing ADC Raytheon TDC1035

3. Pipeline ADC

As mentioned above, the maximum bit width of a direct weighing ADC is 10. To increase the resolution, it is necessary to use other structures. Many of today's high-speed ADCs consist of nodes that sequentially process the signal over several sample clock cycles. In this case, the frequency of appearance of output codes is equal to the frequency of the sampling signal. They are called pipeline-type ADCs.

3.1. Pipeline rough-current ADC (Subranging)

In this case, now the most common method, a group of high-order bits is first converted into digital form (rough conversion). Using a DAC, the received code is converted into an analog signal, which is subtracted from the input. The difference voltage is amplified and supplied to the ADC, which converts a group of low-order bits (precise conversion). The number of such clarifying transformations, and therefore cascades, can be quite large. Low- and high-order ADCs operate simultaneously, sequentially processing incoming samples. The device can use internal ADCs built on different principles - direct weighing or, for example, MagAmps, discussed below.

In Fig. Figure 4 shows the structure of the advanced 12-bit Subranging ADC AD9042 from Analog Devices, which is available in versions with sampling rates of 60 and 41 MHz. The first sample-and-hold circuit, SHA1, stores the signal sample in the usual manner for the duration of the conversion. Its output signal is converted by an ADC, the output code of which is stored in a buffer register and is also used to control the DAC. The SHA2 sample-and-hold circuit is used to prevent the operation of the first ADC from affecting the accuracy of the subsequent part of the device. The DAC signal is subtracted from its output signal. The difference voltage is amplified and stored by the SHA3 sample-and-hold circuit for the time required to operate the second ADC. At correct operation of the first ADC, its error will not exceed one in the least significant bit. The number of bits of the second converter is selected in such a way that the number of bits of the first and second ADCs is one greater than the bit capacity of the ADC as a whole. The excess bit is used to correct the conversion error of the first ADC. To do this, the DAC must have an accuracy no less than that of the ADC as a whole, that is, in this case, 12-bit, and the summing amplifier must have such a gain that the weight of the most significant bit of the second ADC is no less than the least significant bit of the first. In this case, the correcting logic circuit, which is a full adder, will be able to reduce the conversion error to a value corresponding to a given number of ADC bits. A special feature is the use of an ADC of the MagAmps type, which is well developed by the company, and to obtain high linearity and performance, a DAC with 63 current sources, the weighting coefficient of each of which corresponds to a specific code. The technical ideas contained in this structure are used in a number of other Analog Devices products.

Rice. 4. Block diagram of a pipeline ADC with correction logic Analog Devices AD9042

The ADS807 ADC has a similar structure, used by Burr-Brown in all series of high-speed ADCs: 12-bit ADS80X (fastest ADS807 - 53 MHz), 10-bit ADS82X and ADS90X (fastest ADS824 - 70 MHz), 8-bit ADS83X and ADS93X (fastest ADS831 - 80 MHz).

All Texas Instruments high-speed ADCs are also based on this method. Because they use internal direct-weighted (Flash) ADCs, the company calls their structure Samiflash. With the exception of the TLC876, they are all 8-bit and use two internal 4-bit ADCs. The fastest of them is TLV5580 (8 bits, 80 MHz, delay time for the appearance of the output code is 4.5 clock cycles), the most accurate is TLC876 (10 bits, 20 MHz, uses 5 internal two-bit ADCs).

3.2. Multistage with single-bit ADCs

One of the early versions of a pipelined ADC (ripple) consisted of identical stages connected in series. Each stage contained an amplifier, a one-bit DAC and a comparator [X]. The input signal was stored by a sample-and-hold circuit, fed to the first comparator, when it was triggered, the one-bit DAC signal was subtracted from the input signal, amplified by 2 times by the amplifier (to obtain the same sensitivity in all stages) and supplied to the next stage as a difference signal. Thus, each of the stages carried out a single-bit analog-to-digital conversion. The set of signals from the outputs of all comparators represented the result of the transformation, which was recoded by the output logic into a standard form. The conversion time was determined mainly by the time it took for the signal to pass through all stages.

Rice. 5. Block diagram of a one-bit MagAmp ADC - an element of a pipeline ADC

An improved pipeline structure built from single-bit ADCs is called Magnitude Amplifiers, or MagAmps for short, as it uses amplifiers of the absolute value of the signal. Other names are also used. The equivalent cascade circuit of such an ADC is shown in Fig. 5. The comparator determines the sign of the input voltage, according to which it produces an output bit. At the same time, it controls the sign of the gain with which the signal enters the next stage: +2 or –2. The reference voltage VR is summed with the voltage at the switch output, forming a difference signal that goes to the next stage. Unlike the variant described above (ripple), this dependence has jumps only in the derivative, but does not have sharp jumps in amplitude, which helps to achieve a high conversion speed. The main factor making it possible to achieve high conversion speeds was the ability to implement high-speed differential stages with low distortion and accuracy reaching 8 bits without the use of feedback in new current-controlled analog IC structures. Due to the shape of the dependence, this ADC is also called folded, and for the output encoding in the form of a Gray code, it is also called a serial Gray ADC. Due to their manufacturability, these structures are often used in the construction of low-cost ADCs with good characteristics. For example, Analog Devices in its AD9042 12-bit ADCs, the AD922X series with up to 10 MHz sample rate, the dual 8-bit AD9059 with 60 MHz sample rate (5 MSB), and the 8-bit AD9054 with 200 MHz sample rate ( 4 senior digits).

4. About the use of multiphase sampling

When the sampling signals are unstable, which usually manifests itself in the form of their phase jitter, the appearance of characteristic characteristics is observed on signals with a frequency commensurate with the sampling frequency. nonlinear distortion, the greater the higher the rate of change of the signal. Special measures are taken to improve the temporal stability of clock generators, for example, new Hewlett-Packard oscilloscopes use a phase-locked loop shaping circuit, which provides a very stable clock signal.

Often in high-speed ADCs built on various principles, in order to increase the equivalent sampling frequency of the device as a whole, several ADCs are used in parallel on the inputs and samples with a time shift relative to each other. This method, called multiphase sampling, provides significant advantages in conversion speed if the time of recording (sampling) a signal into one physical storage cell is significantly less than the time from the arrival of the sampling signal to the appearance of the signal at the ADC output. For example, in the AD9059 mentioned above, the sample time of the on-chip sample-and-hold circuit is 1 ns, and the minimum interval between sample signals is 16.7 ns. However, this opportunity must be used carefully. Limitations caused by the insufficient stability of the sampling signals and the difference in conversion time for the ADCs included in the device lead to the fact that now most often either the interleaving of only two ADCs implemented on one chip is used, like the AD9058, or this possibility is abandoned altogether, as in new oscilloscopes from Hewlett-Packard.

Literature

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